1. Field of the Invention
The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit (input buffer circuit) that converts an output level from an ECL logic circuit or GaAs logic operating with a negative power supply to a level for a CMOS logic circuit operating with a positive power supply.
2. Background of the Invention
FIG. 5 shows an example of a level conversion circuit of this type in the prior art. An ECL logic circuit (emitter coupled logic circuit) 21 operates with a negative potential VEE (usually -5.2 V to -4.5 V). In contrast to this, a CMOS logic circuit 31 operates between a positive potential VDD (usually +5 V or +3.3 V) and ground. The output of an ECL logic circuit (for example, an open-collector output of an NPN bipolar transistor) 21 is connected to a termination voltage VTT (usually -2 V) via a transmission path 22 and a termination resistance 23. By doing this, ECL levels (usually a high level of -0.9 V and a low level of -1.7 V) appear at the node 24 between transmission path 22 and the termination resistance 23. The AC component obtained at the node 24 is transmitted to an input terminal 25, via a series-connected capacitor 26. The DC bias on the input terminal (usually approximately VDD-2 V) 25 is generated, for example, by dividing a voltage between VDD and ground, using resistances R1 and R2. In PECL-CMOS level conversion circuit 28, an input voltage converted to a positive ECL level (so-called PECL level) is compared with a reference voltage (usually approximately VDD-1.3 V) applied to a reference voltage input terminal 27, and a full-swing CMOS level between VDD and ground is output to the output terminal 29. By making an AC connection in this manner via a series-connected capacitor 26, the signal levels of an ECL logic circuit 21 operating with a negative potential VEE is converted to the signal levels of a CMOS logic circuit 31 operating with a positive potential VDD.
Because the configuration of a circuit of the PECL-CMOS converter 28 is known to persons versed in the art, it will not be described in detail herein.
Another example of a level conversion circuit of the past is the circuit shown in FIG. 6, which was disclosed in the Japanese unexamined Patent Publication (KOKAI) No.10-13209. In this prior art, in order to convert a signal level from an ECL logic circuit 21 operating with a negative potential to a signal level of a CMOS logic circuit 31 operating with a positive potential, the ECL signal is input to a differential circuit that is formed by NPN bipolar transistors (Q1 and Q2), a constant-current source 32, and a load resistance (R3). The output from the load resistance (R3) of the differential circuit is connected to the gate electrode of a pMOS transistor (M3), the source electrode of which is connected to VDD and the drain electrode of which is connected to a resistance (R4). Additionally, the collector electrode of the transistor (Q2) is connected to the drain electrode of the transistor (M3). When transistor (Q2) is off, the transistor (M3) and (R4) operate as a VDD-grounded inverter circuit, the output level of which rises to nearly VDD. When the transistor (Q2) is on, resistance (R4) is pulled down to the ground, so that the output level falls to nearly ground level. Ultimately, the signal levels of an ECL logic circuit 21 operating with a negative potential VEE is converted to the signal levels of a CMOS logic circuit 31 having a full swing CMOS level between a positive potential VDD and ground level.
A first problem associated with the above-noted circuit of the past, however, is that, as shown in FIG. 5, when AC connection is made via a capacitor, the signal being transferred is restricted. That is, it is necessary to process a signal so as to maintain at a mark ratio of 50% in a scrambled signal or an 8B10 coded signal.
The reason for this is that, if the same code level (for example, the logical 0 level) is maintained continuously for a time period that is approximately the same as the RC time constant established by the capacitance of capacitor 26 and the termination resistance 23, the input voltage to the PECL-CMOS level converter reaches the self-bias voltage level, making logical discrimination impossible.
A second problem associated with the above-noted prior art is that, as shown in FIG. 6, while the use of a DC connection solves the first problem described above, a negative power supply must also be applied to the level conversion circuit. Therefore, when using the above-noted circuit as an ASIC input buffer, it is necessary to give special consideration to the application of the positive and negative power supplies (for example, power supply distribution, ESD protection between power supplies, and power-on sequencing restrictions), so that the circuit as shown in FIG. 6 is not suited for standard ASIC design methods.
The third problem is that, in the second prior art shown in FIG. 6, a BiCMOS process is necessary, this generally having a manufacturing cost that is higher than that of a CMOS process.
Accordingly, it is an object of the present invention to improve the above-noted problems of the prior art, by providing a novel level conversion circuit capable of signal transmission from DC, which does not require the application of a negative power supply, which can be implemented using a CMOS process, which is suited for standard ASIC design methods, and which converts the signal levels of an ECL logic circuit operating with a negative potential VEE to the signal levels of a CMOS logic circuit operating with a positive potential VDD.